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» Power Macromodeling for High Level Power Estimation
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DAC
1997
ACM
13 years 11 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm
ISVLSI
2007
IEEE
160views VLSI» more  ISVLSI 2007»
14 years 1 months ago
On the Limitations of Power Macromodeling Techniques
Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as ...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
GLVLSI
1998
IEEE
94views VLSI» more  GLVLSI 1998»
13 years 12 months ago
Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation
Muhammad M. Khellah, Mohamed I. Elmasry
DAC
1997
ACM
13 years 11 months ago
A Power Estimation Framework for Designing Low Power Portable Video Applications
This paper presents a power evaluation framework designed for estimating power consumption of a new video telephone compression standard, ITU-H.263, at the system level. A hierarc...
Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun ...
DAC
1997
ACM
13 years 11 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...