111 search results - page 16 / 23 » Power Optimization in Current Mode Circuits |
ATS
2009
IEEE
13 years 5 months ago
2009
IEEE
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
ARC
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF(p). We use this processor to compare a new algorit...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
—This paper presents a SEPIC PFC converter for driving multiple lighting LED lamps. With the aid of this converter, high power factor and high efficiency can be achieved by a sim...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...