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» Power Optimized Combinational Logic Design
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ISCAPDCS
2008
13 years 9 months ago
Parallel Embedded Systems: Where Real-Time and Low-Power Meet
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
Zdravko Karakehayov, Yu Guo
CASES
2001
ACM
13 years 11 months ago
The emerging power crisis in embedded processors: what can a poor compiler do?
It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, n...
Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John...
INFOCOM
1998
IEEE
13 years 12 months ago
Design of Logical Topologies: A Linear Formulation for Wavelength Routed Optical Networks with No Wavelength Changers
We consider the problem of constructing logical topologies over a wavelength-routed optical network with no wavelength changers. We present a general linear formulation which consi...
Rajesh M. Krishnaswamy, Kumar N. Sivarajan
FPGA
2009
ACM
180views FPGA» more  FPGA 2009»
14 years 2 months ago
Scalable don't-care-based logic optimization and resynthesis
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...
TCAD
2008
115views more  TCAD 2008»
13 years 7 months ago
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...