430 search results - page 35 / 86 » Power Optimized Combinational Logic Design |
FPL
2006
Springer
14 years 1 months ago
2006
Springer
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
TCOM
2008
13 years 10 months ago
2008
This paper proposes a cross-layer optimization framework for the wireless sensor networks. In a wireless sensor network, each sensor makes a local observation of the underlying phy...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
Modern applications for mobile computing require high performance architectures. On the other hand, there are restrictions such as storage or power consumption. The use of recon...
FPGA
2010
ACM
14 years 7 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...