430 search results - page 66 / 86 » Power Optimized Combinational Logic Design |
NOCS
2008
IEEE
14 years 3 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
MICRO
2002
IEEE
13 years 8 months ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
TVLSI
2002
13 years 8 months ago
2002
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
GLVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
GECCO
2005
Springer
14 years 2 months ago
2005
Springer
Self-adaptation of the mutation strengths is a powerful mechanism in evolution strategies (ES), but it can fail. As a consequence premature convergence or ending up in a local opt...