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» Power Optimized Combinational Logic Design
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ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 4 months ago
Energy Characterization of Hardware-Based Data Prefetching
This paper evaluates several hardware-based data prefetching techniques from an energy perspective, and explores their energy/performance tradeoffs. We present detailed simulation...
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Kri...
186
Voted
ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
15 years 10 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
16 years 9 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
ISSA
2004
15 years 8 months ago
High Data Rate 8-Bit Crypto Processor
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
Sheikh Muhammad Farhan
194
Voted
DMDW
2000
161views Management» more  DMDW 2000»
15 years 8 months ago
View materialization for nested GPSJ queries
View materialization is a central issue in logical design of data warehouses since it is one of the most powerful techniques to improve the response to the workload. Most approach...
Matteo Golfarelli, Stefano Rizzi