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» Power and performance optimization at the system level
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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
13 years 7 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
CASES
2008
ACM
15 years 6 months ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...
BMCBI
2006
88views more  BMCBI 2006»
15 years 4 months ago
Effect of various normalization methods on Applied Biosystems expression array system data
Background: DNA microarray technology provides a powerful tool for characterizing gene expression on a genome scale. While the technology has been widely used in discovery-based m...
Catalin C. Barbacioru, Yulei Wang, Roger D. Canale...
156
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JSAC
2010
194views more  JSAC 2010»
15 years 3 months ago
Burst communication by means of buffer allocation in body sensor networks: Exploiting signal processing to reduce the number of
Abstract—Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. Such platforms use inertial information of their...
Hassan Ghasemzadeh, Vitali Loseu, Sarah Ostadabbas...
DSN
2003
IEEE
15 years 10 months ago
ICR: In-Cache Replication for Enhancing Data Cache Reliability
Processor caches already play a critical role in the performance of today’s computer systems. At the same time, the data integrity of words coming out of the caches can have ser...
Wei Zhang 0002, Sudhanva Gurumurthi, Mahmut T. Kan...