1850 search results - page 273 / 370 » Power and performance optimization at the system level |
125
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern...
131
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IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
The Parallel-Horus framework, developed at the University of Amsterdam, is a unique software architecture that allows non-expert parallel programmers to develop fully sequential m...
162
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ALP
1992
Springer
15 years 8 months ago
1992
Springer
Rewriting is a computational paradigm that specifies the actions, but not the control. We introduce a hierarchical structure repreat a high level of abstraction, a form of control....
154
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ICCD
2007
IEEE
15 years 8 months ago
2007
IEEE
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
164
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SENSYS
2004
ACM
15 years 10 months ago
2004
ACM
Habitat and environmental monitoring is a driving application for wireless sensor networks. We present an analysis of data from a second generation sensor networks deployed during...