734 search results - page 19 / 147 » Power balanced pipelines |
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
SBCCI
2003
ACM
14 years 1 months ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
CF
2008
ACM
13 years 10 months ago
2008
ACM
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
ISPAN
1997
IEEE
14 years 24 days ago
1997
IEEE
This paper presents a strategy for efficiently rendering time-varying volume data on a distributed-memory parallel computer. Visualizing time-varying volume data take both large s...
ICIP
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...