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ICISC
2009
125views Cryptology» more  ICISC 2009»
13 years 6 months ago
Power Analysis of Single-Rail Storage Elements as Used in MDPL
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 3 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 2 months ago
Reliability-Aware SOC Voltage Islands Partition and Floorplan
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
SOCC
2008
IEEE
233views Education» more  SOCC 2008»
14 years 3 months ago
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
Yang Sun, Joseph R. Cavallaro
GIS
2008
ACM
14 years 9 months ago
Low-cost orthographic imagery
Commercial aerial imagery websites, such as Google Maps, MapQuest, Microsoft Virtual Earth, and Yahoo! Maps, provide high- seamless orthographic imagery for many populated areas, ...
Peter Pesti, Jeremy Elson, Jon Howell, Drew Steedl...