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2001
13 years 10 months ago
High-speed Parameterisable Hough Transform Using Reconfigurable Hardware
Recent developments in reconfigurable hardware technologies have offered high-density high-speed devices with the ability for custom computing whilst maintaining the flexibility o...
Dixon D. S. Deng, Hossam A. ElGindy
IAJIT
2010
107views more  IAJIT 2010»
13 years 7 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
MEMOCODE
2010
IEEE
13 years 6 months ago
Elastic systems
Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new corr...
Jordi Cortadella, Marc Galceran Oms, Michael Kishi...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 6 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
PROCEDIA
2010
140views more  PROCEDIA 2010»
13 years 3 months ago
Theoretical enzyme design using the Kepler scientific workflows on the Grid
One of the greatest challenges in computational chemistry is the design of enzymes to catalyze non-natural chemical reactions. We focus on harnessing the distributed parallel comp...
Jianwu Wang, Prakashan Korambath, Seonah Kim, Scot...