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ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
TC
2008
13 years 8 months ago
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
Sung Woo Chung, Kevin Skadron
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
13 years 14 days ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
HPCA
2009
IEEE
14 years 3 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...
AGTIVE
2003
Springer
14 years 2 months ago
Specifying Pointer Structures by Graph Reduction
Graph-reduction specifications (GRSs) are a powerful new method for specifying classes of pointer data structures (shapes). They cover important shapes, like various forms of bal...
Adam Bakewell, Detlef Plump, Colin Runciman