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FPL
2003
Springer
114views Hardware» more  FPL 2003»
14 years 23 days ago
Power Analysis of FPGAs: How Practical is the Attack?
Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve en...
François-Xavier Standaert, Loïc van Ol...
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
14 years 2 months ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
ICASSP
2011
IEEE
12 years 11 months ago
Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems
—Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two...
Subhanshu Gupta, Yi Tang, Kuang-Wei Cheng, Jeyanan...
CODES
2008
IEEE
13 years 9 months ago
Power reduction via macroblock prioritization for power aware H.264 video applications
As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portab...
Michael A. Baker, Viswesh Parameswaran, Karam S. C...
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 5 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias