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» Power distribution techniques for dual VDD circuits
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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 2 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ECCTD
2011
72views more  ECCTD 2011»
12 years 8 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic
IPPS
2007
IEEE
14 years 2 months ago
A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA
This work addresses the problem of information leakage of cryptographic devices, by using the reconfiguration technique allied to an RNS based arithmetic. The information leaked b...
Daniel Mesquita, Benoît Badrignans, Lionel T...
ICUMT
2009
13 years 6 months ago
Cooperative robust sequential detection algorithms for Spectrum Sensing in Cognitive Radio
Abstract-- We consider the problem of Spectrum Sensing in Cognitive Radio Networks. In our previous work we have developed DualCUSUM, a distributed algorithm for change detection a...
ArunKumar Jayaprakasam, Vinod Sharma
HPCA
2004
IEEE
14 years 9 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...