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» Power minimization using control generated clocks
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ACSC
2003
IEEE
14 years 1 months ago
Communication Performance Issues for Two Cluster Computers
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
Francis Vaughan, Duncan A. Grove, Paul D. Coddingt...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
14 years 26 days ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
CDC
2008
IEEE
180views Control Systems» more  CDC 2008»
14 years 3 months ago
Opacity-enforcing supervisory strategies for secure discrete event systems
ā€” Initial-state opacity emerges as a key property in numerous security applications of discrete event systems including key-stream generators for cryptographic protocols. Speciļ¬...
Anooshiravan Saboori, Christoforos N. Hadjicostis
ISCC
2007
IEEE
131views Communications» more  ISCC 2007»
14 years 2 months ago
SIP and MIPv6: Cross-Layer Mobility
Terminal mobility may be handled at different layers. Though the MIPv6 protocol is the strongest candidate for handling mobility in next generation networks, mobility management f...
Rui Prior, Susana Sargento
GECCO
2007
Springer
167views Optimization» more  GECCO 2007»
14 years 2 months ago
Genetically designed heuristics for the bin packing problem
The bin packing problem (BPP) is a real-world problem that arises in diļ¬€erent industrial applications related to minimization of space or time. The aim of this research is to au...
Oana Muntean