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» Power minimization using control generated clocks
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IPPS
2007
IEEE
14 years 2 months ago
Analysis of a Computational Biology Simulation Technique on Emerging Processing Architectures
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
Jeremy S. Meredith, Sadaf R. Alam, Jeffrey S. Vett...
CEC
2003
IEEE
14 years 1 months ago
An evolutionary approach for reducing the switching activity in address buses
In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
14 years 11 days ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
DCOSS
2008
Springer
13 years 10 months ago
Decoding Code on a Sensor Node
Abstract. Wireless sensor networks come of age and start moving out of the laboratory into the field. As the number of deployments is increasing the need for an efficient and relia...
Pascal von Rickenbach, Roger Wattenhofer
JSAC
2008
125views more  JSAC 2008»
13 years 8 months ago
Nonbinary LDPC Coding for Multicarrier Underwater Acoustic Communication
Recently, multicarrier modulation in the form of orthogonal frequency division multiplexing (OFDM) has been shown feasible for underwater acoustic communications via effective algo...
Jie Huang, Shengli Zhou, Peter Willett