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» Power minimization using control generated clocks
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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
HICSS
2010
IEEE
145views Biometrics» more  HICSS 2010»
14 years 3 months ago
Dynamics of an Economics Model for Generation Coupled to the OPA Power Transmission Model
In this paper we explore the interaction between a dynamic model of the power transmission system (OPA) and a simple economic model of power generation development. Despite the si...
Benjamin A. Carreras, David E. Newman, Matthew Zei...
JACM
2002
87views more  JACM 2002»
13 years 8 months ago
Bounded concurrent timestamp systems using vector clocks
Abstract. Shared registers are basic objects used as communication mediums in asynchronous concurrent computation. A concurrent timestamp system is a higher typed communication obj...
Sibsankar Haldar, Paul M. B. Vitányi
ICCD
2001
IEEE
144views Hardware» more  ICCD 2001»
14 years 5 months ago
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
TWC
2010
13 years 3 months ago
Delay-Minimal Transmission for Average Power Constrained Multi-Access Communications
We investigate the problem of minimizing the overall transmission delay of packets in a multi-access wireless communication system, where the transmitters have average power constr...
Jing Yang, Sennur Ulukus