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» Power minimization using control generated clocks
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ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
14 years 1 months ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
14 years 18 days ago
Analog Micropipeline Rings for High Precision Timing
I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at...
Scott Fairbanks, Simon W. Moore
MOBICOM
2009
ACM
14 years 3 months ago
A quorum-based framework for establishing control channels in dynamic spectrum access networks
Establishing a control channel for medium access control is a challenging problem in multi-channel and dynamic spectrum access (DSA) networks. In the design of multi-channel MAC p...
Kaigui Bian, Jung Min Park, Ruiliang Chen
TC
2008
13 years 8 months ago
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
Sung Woo Chung, Kevin Skadron
CGI
1996
IEEE
14 years 1 months ago
Recent Advances in Image Morphing
Image morphing has been the subject of much attention in recent years. It has proven to be a powerful visual effects tool in film and television, depicting the fluid transformatio...
George Wolberg