732 search results - page 57 / 147 » Power minimization using control generated clocks |
IJNSEC
2011
13 years 3 months ago
2011
We introduce some modifications to the widely deployed Kerberos authentication protocol. The principle’s secretkey will be independent of the user password to overcome the weak...
TVLSI
2002
13 years 8 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
TIM
2010
13 years 3 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
FPT
2005
IEEE
14 years 2 months ago
2005
IEEE
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
CDC
2009
IEEE
14 years 3 days ago
2009
IEEE
—We consider the management of electric vehicle (EV) loads within a market-based Electric Power System Control Area. EV load management achieves cost savings in both (i) EV batte...