Sciweavers

82 search results - page 16 / 17
» Power reduction techniques for Dynamically Reconfigurable Pr...
Sort
View
PLDI
2010
ACM
14 years 19 days ago
Decoupled lifeguards: enabling path optimizations for dynamic correctness checking tools
Dynamic correctness checking tools (a.k.a. lifeguards) can detect a wide array of correctness issues, such as memory, security, and concurrency misbehavior, in unmodified executa...
Olatunji Ruwase, Shimin Chen, Phillip B. Gibbons, ...
IEEEPACT
2005
IEEE
14 years 1 months ago
Compiler Directed Early Register Release
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
ICFP
2010
ACM
13 years 8 months ago
Lazy tree splitting
Nested data-parallelism (NDP) is a declarative style for programming irregular parallel applications. NDP languages provide language features favoring the NDP style, efficient com...
Lars Bergstrom, Mike Rainey, John H. Reppy, Adam S...
DAC
2009
ACM
14 years 8 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 1 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang