82 search results - page 7 / 17 » Power reduction techniques for Dynamically Reconfigurable Pr... |
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
LCPC
2004
Springer
14 years 29 days ago
2004
Springer
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...