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» Power scalable processing using distributed arithmetic
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ASPLOS
2000
ACM
14 years 2 months ago
Communication Scheduling
The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect betw...
Peter R. Mattson, William J. Dally, Scott Rixner, ...
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
14 years 3 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
14 years 3 months ago
Low power block based FIR filtering cores
— The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals t...
Ahmet T. Erdogan, Tughrul Arslan
ISCAPDCS
2001
13 years 11 months ago
AMOS-SDDS: A Scalable Distributed Data Manager for Windows Multicomputers
Known parallel DBMS offer at present only static partitioning schemes. Adding a storage node is then a cumbersome operation that typically requires the manual data redistribution....
Yakham Ndiaye, Aly Wane Diene, Witold Litwin, Tore...
PVM
2010
Springer
13 years 8 months ago
PMI: A Scalable Parallel Process-Management Interface for Extreme-Scale Systems
Parallel programming models on large-scale systems require a scalable system for managing the processes that make up the execution of a parallel program. The process-management sys...
Pavan Balaji, Darius Buntinas, David Goodell, Will...