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ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 1 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
CHES
2008
Springer
144views Cryptology» more  CHES 2008»
13 years 9 months ago
Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs
Abstract. This paper proposes new chosen-message power-analysis attacks against public-key cryptosystems based on modular exponentiation, which use specific input pairs to generate...
Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Ak...
ARITH
2001
IEEE
13 years 11 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
ICASSP
2011
IEEE
12 years 11 months ago
Stochastic optimization based on the Laplace transform order with applications to precoder designs
Stochastic optimization arising from precoding in a multi-antenna fading channel with channel mean feedback to maximize data rates is important but challenging. The use of relayin...
Minhua Ding, Keith Q. T. Zhang
ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
14 years 1 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll