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DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 1 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
INFOCOM
2005
IEEE
14 years 29 days ago
TCAM-based distributed parallel packet classification algorithm with range-matching solution
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...
Kai Zheng, Hao Che, Zhijun Wang, Bin Liu
DRMTICS
2005
Springer
14 years 27 days ago
A Vector Approach to Cryptography Implementation
The current deployment of Digital Right Management (DRM) schemes to distribute protected contents and rights is leading the way to massive use of sophisticated embedded cryptograph...
Jacques J. A. Fournier, Simon W. Moore
ICS
2005
Tsinghua U.
14 years 27 days ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
SAMOS
2005
Springer
14 years 26 days ago
Automatic ADL-Based Assembler Generation for ASIP Programming Support
Abstract. Systems-on-Chip (SoCs) may be built upon general purpose CPUs or application-specific instruction-set processors (ASIPs). On the one hand, ASIPs allow a tradeoff betwee...
Leonardo Taglietti, José O. Carlomagno Filh...