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» Power-Aware Speed Scaling in Processor Sharing Systems
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211
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JCSC
2002
129views more  JCSC 2002»
15 years 5 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
189
Voted
IPPS
2009
IEEE
16 years 23 days ago
Designing multi-leader-based Allgather algorithms for multi-core clusters
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
Krishna Chaitanya Kandalla, Hari Subramoni, Gopala...
145
Voted
IPPS
2000
IEEE
15 years 10 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
HPCA
2007
IEEE
16 years 6 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
172
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IFIP
1998
Springer
15 years 10 months ago
Migrating Objects in Electronic Commerce Applications
Electronic Commerce is a field of application that is distributed by nature where different parties share information and work concurrently and cooperatively on objects, potential...
Marko Boger