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» Power-Aware Speed Scaling in Processor Sharing Systems
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CODES
2008
IEEE
13 years 9 months ago
Power reduction via macroblock prioritization for power aware H.264 video applications
As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portab...
Michael A. Baker, Viswesh Parameswaran, Karam S. C...
IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
SIGMETRICS
2010
ACM
178views Hardware» more  SIGMETRICS 2010»
14 years 10 days ago
Optimality, fairness, and robustness in speed scaling designs
System design must strike a balance between energy and performance by carefully selecting the speed at which the system will run. In this work, we examine fundamental tradeoffs i...
Lachlan L. H. Andrew, Minghong Lin, Adam Wierman
CORR
2010
Springer
177views Education» more  CORR 2010»
13 years 4 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
HPCA
1999
IEEE
13 years 12 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve