Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors

Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not exploit common instruction-level parallelism (ILP) features, consequently exhibiting large errors when used to model current systems. A few newer simulators model current ILP processors in detail, but we find them to be about ten times slower. We propose a new simulation technique, based on a novel adaptation of direct execution, that alleviates this accuracy vs. speed tradeoff. We compare the speed and accuracy of our new simulator, DirectRSIM, with three other simulators

• Type: Conference
• Year: 1999
• Where: HPCA
• Authors: Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
• Keywords: Distributed And Parallel Computing, HPCA 1999, ILP Processors, Simulator, Simulators Model