Sciweavers

172 search results - page 7 / 35
» Power-Aware Speed Scaling in Processor Sharing Systems
Sort
View
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
13 years 11 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
CCGRID
2003
IEEE
14 years 25 days ago
The Performance of Processor Co-Allocation in Multicluster Systems
In systems consisting of multiple clusters of processors which are interconnected by relatively slow communication links and which employ space sharing for scheduling jobs, such a...
Anca I. D. Bucur, Dick H. J. Epema
LCTRTS
2007
Springer
14 years 1 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...
ICCAD
2003
IEEE
210views Hardware» more  ICCAD 2003»
14 years 4 months ago
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems
Energy consumption is an important performance parameter for portable and wireless embedded systems. However, energy consumption must be carefully balanced with real-time responsi...
Vishnu Swaminathan, Krishnendu Chakrabarty
PODC
2006
ACM
14 years 1 months ago
Grouped distributed queues: distributed queue, proportional share multiprocessor scheduling
We present Grouped Distributed Queues (GDQ), the first proportional share scheduler for multiprocessor systems that scales well with a large number of processors and processes. G...
Bogdan Caprita, Jason Nieh, Clifford Stein