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TC
2008
13 years 10 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
JCM
2007
115views more  JCM 2007»
13 years 10 months ago
eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions
— Radio Frequency Identification (RFID) technology has a lot of potential to improve visibility across the supply chain and automate the business processes. This paper describes ...
Franco Fummi, Giovanni Perbellini
TWC
2008
114views more  TWC 2008»
13 years 10 months ago
Two dimensional cross-layer optimization for packet transmission over fading channel
In this paper a single-input-single-output wireless data transmission system with adaptive modulation and coding over correlated fading channel is considered, where run-time power ...
Xiaofeng Bai, Abdallah Shami
JAL
2002
71views more  JAL 2002»
13 years 9 months ago
A primal-dual schema based approximation algorithm for the element connectivity problem
The element connectivity problem falls in the category of survivable network design problems { it is intermediate to the versions that ask for edge-disjoint and vertex-disjoint pa...
Kamal Jain, Ion I. Mandoiu, Vijay V. Vazirani, Dav...
TCAD
2002
145views more  TCAD 2002»
13 years 9 months ago
Automatic generation of synthetic sequential benchmark circuits
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil