426 search results - page 10 / 86 » Power-Sensitive Multithreaded Architecture |
SBACPAD
2007
IEEE
14 years 2 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
COORDINATION
2005
Springer
14 years 2 months ago
2005
Springer
Architectural descriptions can provide support for a formal representation of the structure and the overall behavior of software systems, which is suitable for an early assessment ...
ARC
2007
Springer
14 years 19 days ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectivel...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Programs with irregular patterns of dynamic data structures and/or those with complicated control structures such as recursion are notoriously difficult to parallelize efficient...