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FCCM
2007
IEEE
101views VLSI» more  FCCM 2007»
14 years 3 months ago
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...
IPPS
2010
IEEE
13 years 6 months ago
A GPU-inspired soft processor for high-throughput acceleration
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
Jeffrey Kingyens, J. Gregory Steffan
VLSID
2001
IEEE
132views VLSI» more  VLSID 2001»
14 years 9 months ago
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL component...
Nachiketh R. Potlapally, Michael S. Hsiao, Anand R...
GCC
2003
Springer
14 years 1 months ago
Distributed Computation for Diffusion Problem in a P2P-Enhanced Computing System
Basic exploration of diffusion equation solvers in distributed computing systems has been a very important issue for computational fluid dynamics (CFD). This paper presents a funda...
Jun Ni, Lili Huang, Tao He, Yongxiang Zhang, Shaow...
ICS
2009
Tsinghua U.
14 years 3 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...