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» Power-aware Multimedia Systems using Run-time Prediction
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IISWC
2006
IEEE
14 years 2 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
CGO
2004
IEEE
14 years 9 days ago
A Compiler Scheme for Reusing Intermediate Computation Results
Recent research has shown that programs often exhibit value locality. Such locality occurs when a code segment, although executed repeatedly in the program, takes only a small num...
Yonghua Ding, Zhiyuan Li
LCTRTS
2005
Springer
14 years 2 months ago
Efficient application migration under compiler guidance
Mobile computing based upon wireless technology as the interconnect and PDAs, Web-enabled cell phones etc. as the end devices provide a rich infrastructure for anywhere, anytime i...
Kun Zhang, Santosh Pande
ASPLOS
2004
ACM
14 years 2 months ago
Compiler orchestrated prefetching via speculation and predication
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
Rodric M. Rabbah, Hariharan Sandanagobalane, Mongk...
CASES
2007
ACM
14 years 17 days ago
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter