46 search results - page 6 / 10 » Power-aware issue queue design for speculative instructions |
ISHPC
2003
Springer
14 years 1 months ago
2003
Springer
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
HPCA
1996
IEEE
14 years 20 days ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
MICRO
1994
IEEE
14 years 19 days ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
IBMRD
2006
13 years 8 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...