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IPPS
2010
IEEE
13 years 5 months ago
Servet: A benchmark suite for autotuning on multicore clusters
Abstract--The growing complexity in computer system hierarchies due to the increase in the number of cores per processor, levels of cache (some of them shared) and the number of pr...
Jorge González-Domínguez, Guillermo ...
PLDI
2003
ACM
14 years 26 days ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
NIPS
2007
13 years 9 months ago
Variational inference for Markov jump processes
Markov jump processes play an important role in a large number of application domains. However, realistic systems are analytically intractable and they have traditionally been ana...
Manfred Opper, Guido Sanguinetti
CASES
2008
ACM
13 years 9 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
14 years 4 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood