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DAC
2005
ACM
13 years 10 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
DAC
2004
ACM
14 years 9 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
CLUSTER
2008
IEEE
14 years 3 months ago
Divisible load scheduling with improved asymptotic optimality
—Divisible load model allows scheduling algorithms that give nearly optimal makespan with practical computational complexity. Beaumont et al. have shown that their algorithm prod...
Reiji Suda
EVOW
2008
Springer
13 years 10 months ago
Multiobjective Prototype Optimization with Evolved Improvement Steps
Recently, a new iterative optimization framework utilizing an evolutionary algorithm called "Prototype Optimization with Evolved iMprovement Steps" (POEMS) was introduced...
Jirí Kubalík, Richard Mordinyi, Stef...
ATS
2004
IEEE
109views Hardware» more  ATS 2004»
14 years 11 days ago
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterj...