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HOTOS
2003
IEEE
14 years 2 months ago
Cassyopia: Compiler Assisted System Optimization
Execution of a program almost always involves multiple address spaces, possibly across separate machines. Here, an approach to reducing such costs using compiler optimization tech...
Mohan Rajagopalan, Saumya K. Debray, Matti A. Hilt...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 2 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
14 years 8 days ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 8 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
14 years 28 days ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita