Sciweavers

298 search results - page 56 / 60
» Predictable Embedded Multiprocessor System Design
Sort
View
HOST
2009
IEEE
14 years 1 months ago
Detecting Trojan Circuit Attacks
Abstract—Rapid advances in integrated circuit (IC) development predicted by Moore’s Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries ...
Gedare Bloom, Bhagirath Narahari, Rahul Simha
RTAS
2006
IEEE
14 years 21 days ago
Real-Time Scheduling on Multicore Platforms
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
James H. Anderson, John M. Calandrino, UmaMaheswar...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 9 days ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
RTAS
1998
IEEE
13 years 11 months ago
End-Host Architecture for QoS-Adaptive Communication
Proliferation of communication-intensive real-time applications with elastic" timeliness constraints, such as streaming stored video, requires a new design for endhost commun...
Tarek F. Abdelzaher, Kang G. Shin
RTAS
2008
IEEE
14 years 1 months ago
A Modular Worst-case Execution Time Analysis Tool for Java Processors
Recent technologies such as the Real-Time Specification for Java promise to bring Java’s advantages to real-time systems. While these technologies have made Java more predictab...
Trevor Harmon, Martin Schoeberl, Raimund Kirner, R...