86 search results - page 7 / 18 » Predictable Instruction Caching for Media Processors |
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded...
ICS
1995
Tsinghua U.
13 years 12 months ago
1995
Tsinghua U.
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
MICRO
1999
IEEE
14 years 21 days ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
EUROPAR
1999
Springer
14 years 20 days ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
MICRO
1994
IEEE
14 years 15 days ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...