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» Predictable Out-of-Order Execution Using Virtual Traces
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HCW
1999
IEEE
13 years 11 months ago
Metacomputing with MILAN
The MILAN project, a joint effort involving Arizona State University and New York University, has produced and validated fundamental techniques for the realization of efficient, r...
Arash Baratloo, Partha Dasgupta, Vijay Karamcheti,...
IPCCC
1999
IEEE
13 years 11 months ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
JVM
2004
165views Education» more  JVM 2004»
13 years 8 months ago
Using Hardware Performance Monitors to Understand the Behavior of Java Applications
Modern Java programs, such as middleware and application servers, include many complex software components. Improving the performance of these Java applications requires a better ...
Peter F. Sweeney, Matthias Hauswirth, Brendon Caho...
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 23 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
CONEXT
2009
ACM
13 years 8 months ago
Virtually eliminating router bugs
Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. Rather than simply crashing the router, bugs can violate protocol semant...
Eric Keller, Minlan Yu, Matthew Caesar, Jennifer R...