492 search results - page 22 / 99 » Predictable performance in SMT processors |
SBACPAD
2004
IEEE
13 years 10 months ago
2004
IEEE
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes br...
DAGSTUHL
2004
13 years 10 months ago
2004
Abstract. This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design ...
SAC
2006
ACM
14 years 2 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
CGO
2004
IEEE
14 years 19 days ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
AES
2011
Springer
12 years 9 months ago
2011
Springer
We propose a model for describing and predicting the parallel performance of a broad class of parallel numerical software on distributed memory architectures. The purpose of this ...