Sciweavers

492 search results - page 65 / 99
» Predictable performance in SMT processors
Sort
View
IEEEPACT
2002
IEEE
15 years 8 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
PPOPP
2009
ACM
16 years 3 months ago
Mapping parallelism to multi-cores: a machine learning based approach
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
Zheng Wang, Michael F. P. O'Boyle
HIPC
2007
Springer
15 years 9 months ago
Experiments with a Parallel External Memory System
Abstract. The theory of bulk-synchronous parallel computing has produced a large number of attractive algorithms, which are provably optimal in some sense, but typically require th...
Mohammad R. Nikseresht, David A. Hutchinson, Anil ...
INFOCOM
2002
IEEE
15 years 8 months ago
Scheduling Processing Resources in Programmable Routers
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...
Prashanth Pappu, Tilman Wolf
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 6 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...