Sciweavers

492 search results - page 76 / 99
» Predictable performance in SMT processors
Sort
View
CASES
2006
ACM
14 years 1 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
TVLSI
2008
150views more  TVLSI 2008»
13 years 7 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
PLDI
2003
ACM
14 years 24 days ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
MICRO
2007
IEEE
135views Hardware» more  MICRO 2007»
14 years 1 months ago
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
Christophe Dubach, Timothy M. Jones, Michael F. P....
ICS
2007
Tsinghua U.
14 years 1 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow