492 search results - page 84 / 99 » Predictable performance in SMT processors |
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
The least recently used (LRU) replacement policy performs poorly in the last-level cache (LLC) because temporal locality of memory accesses is filtered by first and second level...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Researchers have recently proposed coupling small- to mediumscale multiprocessors to build large-scale shared memory machines, known as multigrain shared memory systems. Multigrai...
RTAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
ECRTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
RV
2009
Springer
14 years 1 days ago
2009
Springer
Monitoring of software’s execution is crucial in numerous software development tasks. Current monitoring efforts generally require extensive instrumentation of the software or d...