Abstract--Limited preemption scheduling has been introduced as a viable alternative to non-preemptive and fullypreemptive scheduling when reduced blocking times need to coexist wit...
Marko Bertogna, Giorgio C. Buttazzo, Mauro Marinon...
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
In the design of hard real-time systems, the feasibility of the task set is one of the primary concerns. However, in embedded systems with scarce resources, optimizing resource us...
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...