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ARCS
2010
Springer
14 years 16 days ago
Complexity-Effective Rename Table Design for Rapid Speculation Recovery
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
Görkem Asilioglu, Emine Merve Kaya, Oguz Ergi...
HPCA
2004
IEEE
14 years 8 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
PLDI
2004
ACM
14 years 1 months ago
Balancing register allocation across threads for a multithreaded network processor
+ Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network p...
Xiaotong Zhuang, Santosh Pande
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 8 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ICCAD
2001
IEEE
126views Hardware» more  ICCAD 2001»
14 years 4 months ago
Constraint Satisfaction for Relative Location Assignment and Scheduling
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Je...