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DSRT
2008
IEEE
14 years 2 months ago
An Adaptive Energy-Conserving Strategy for Parallel Disk Systems
In the past decade parallel disk systems have been highly scalable and able to alleviate the problem of disk I/O bottleneck, thereby being widely used to support a wide range of d...
Mais Nijim, Adam Manzanares, Xiao Qin
TPDS
1998
129views more  TPDS 1998»
13 years 7 months ago
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics
—Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconn...
W. Stephen Lacy, José Cruz-Rivera, D. Scott...
AINA
2007
IEEE
14 years 2 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
CASES
2005
ACM
13 years 9 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 24 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...