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MEMOCODE
2010
IEEE
13 years 5 months ago
A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
Patrick O'Neil Meredith, Michael Katelman, Jos&eac...
SIGSOFT
2007
ACM
14 years 8 months ago
Quantitative verification: models techniques and tools
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
Marta Z. Kwiatkowska
CORR
2011
Springer
179views Education» more  CORR 2011»
13 years 2 months ago
An overview of Ciao and its design philosophy
We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An impor...
Manuel V. Hermenegildo, Francisco Bueno, Manuel Ca...
DAC
2001
ACM
14 years 8 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
POPL
2008
ACM
14 years 7 months ago
A theory of contracts for web services
Contracts are behavioural descriptions of Web services. We devise a theory of contracts that formalises the compatibility of a client to a service, and the safe replacement of a s...
Giuseppe Castagna, Nils Gesbert, Luca Padovani