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» Procedural Modeling of Interconnected Structures
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ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
14 years 1 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
EMNLP
2008
13 years 9 months ago
Sampling Alignment Structure under a Bayesian Translation Model
We describe the first tractable Gibbs sampling procedure for estimating phrase pair frequencies under a probabilistic model of phrase alignment. We propose and evaluate two nonpar...
John DeNero, Alexandre Bouchard-Côté,...
CRITIS
2007
13 years 9 months ago
Modeling and Simulating Information Security Management
Security Management is a complex task. It requires several interconnected activities: designing, implementing and maintaining a robust technical infrastructure, developing suitable...
Jose Maria Sarriegi, Javier Santos, Jose M. Torres...
ACSD
2001
IEEE
83views Hardware» more  ACSD 2001»
13 years 11 months ago
Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems
We describe a framework where formal models can be rigorously defined and compared, and their interconnections can be unambiguously specified. We use trace algebra and trace struc...
Jerry R. Burch, Roberto Passerone, Alberto L. Sang...
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
13 years 11 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden