468 search results - page 79 / 94 » Process Migration Effects on Memory Performance of Multiproc... |
ISQED
2002
IEEE
14 years 14 days ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
SIPS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Long initial access cycles of SDRAM are the major performance burden of motion compensation in a video decoder. To minimize its effect while improve overall available memory ba...
COR
2008
13 years 7 months ago
2008
This paper presents a tabu search metaheuristic algorithm for the automatic generation of structural software tests. It is a novel work since tabu search is applied to the automat...
USENIX
2003
13 years 9 months ago
2003
We present an in-kernel disk prefetcher which uses speculative execution to determine what data an application is likely to require in the near future. By placing our design withi...
ICPP
2003
IEEE
14 years 25 days ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...