154 search results - page 27 / 31 » Process Scheduling for Performance Estimation and Synthesis ... |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
EUROMICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
Getting business stakeholders’ goals formulated clearly and project scope defined realistically increases the chance of success for any application development process. As a cons...
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
CASES
2001
ACM
14 years 7 days ago
2001
ACM
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...